Investigation of current flow during wafer-level CDM using real-time probing

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the ind...

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Bibliographic Details
Published inElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2010 pp. 1 - 10
Main Authors Jack, N, Shukla, V, Rosenbaum, E
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2010
Subjects
Current measurement
Probes
Radio frequency
Real time systems
Semiconductor device measurement
Stress
Voltage measurement
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Summary:Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.