Low-Latency Implementation of Coordinate Conversion in Virtex II pro FPGA

The paper presents a low-latency implementation of Cartesian-polar coordinate conversion in a Virtex II pro FPGA. The accuracy and resource consumption of the module is comparable to the one obtained with the Xilinx CORDIC IP Core, but the latency has been reduced to 65%. The application of the conv...

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Bibliographic Details
Published in2007 14th International Conference on Mixed Design of Integrated Circuits and Systems pp. 120 - 123
Main Authors Jablonski, G., Przygoda, K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2007
Subjects
Arcus tangent
Computer arithmetic
Computer science
CORDIC
Cosine
Field programmable gate arrays
FPGA
Microelectronics
Sine
Square root
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Summary:The paper presents a low-latency implementation of Cartesian-polar coordinate conversion in a Virtex II pro FPGA. The accuracy and resource consumption of the module is comparable to the one obtained with the Xilinx CORDIC IP Core, but the latency has been reduced to 65%. The application of the conversion module to the cavity detuning computation in low-level radio frequency control system for a FLASH accelerator has been also presented.
ISBN:9788392263241
8392263243
DOI:10.1109/MIXDES.2007.4286132