Realizing Boolean Functions Using Probabilistic Spin Logic (PSL)

Probabilistic Spin Logic (PSL) is a novel computing model that can be implemented using stochastic units (called p-bits) such as low-barrier nanomagnets. A PSL can exhibit accuracy which is comparable to a conventional digital circuit. Remarkably, a PSL can also be exploited to compute the inverse o...

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Bibliographic Details
Published in2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) pp. 508 - 509
Main Authors Agarwal, Vaibhav, Saurabh, Sneh
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2019
Subjects
Boolean function
Boolean functions
Computational modeling
Digital circuits
Integrated circuit interconnections
Logic gates
P-bits
Probabilistic logic
Simulation
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Summary:Probabilistic Spin Logic (PSL) is a novel computing model that can be implemented using stochastic units (called p-bits) such as low-barrier nanomagnets. A PSL can exhibit accuracy which is comparable to a conventional digital circuit. Remarkably, a PSL can also be exploited to compute the inverse of a function. In this paper, using simulations, we examine the application of PSL in realizing Boolean functions. We propose a methodology to implement any Boolean function given in Conjunctive Normal Form (CNF) using PSL. Our methodology is based on synthesizing a given function in terms of NOT/AND/OR gates and deriving appropriate interconnections between p-bits. Further, we demonstrate the application of PSL in computing the inverse of a given function.
ISSN:2380-6923
DOI:10.1109/VLSID.2019.00110