Resource constrained VLSI architecture for implantable neural data compression systems

• Published in: 2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1481 - 1484
• Main Authors: Kamboh, A.M., Oweiss, K.G., Mason, A.J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Bandwidth; Circuits; Compaction; Data compression; Discrete wavelet transforms; Microelectrodes; Performance analysis; Telemetry; Time frequency analysis; Very large scale integration
• ISBN: 1424438276; 9781424438273
• ISSN: 0271-4302
• DOI: 10.1109/ISCAS.2009.5118047

Neural recordings from high-density microelectrode arrays implanted in the cortex require time-frequency domain processing to alleviate the data telemetry bottlenecks of bandwidth and power. Our previous work has shown that the energy compaction capability of the discrete wavelet transform (DWT) offers a practical data compression solution that faithfully preserves the information in the neural signals. This paper presents a complete compression system including both lossy and lossless compression schemes, namely the DWT and run length encoding. Performance tradeoffs and key design decisions for implantable applications are analyzed. A 32-channel, 4-level version of the circuit is presented. Custom designed in 0.5 mum CMOS, occupying only 5.75 mm 2 and consuming 3mW of power (95 muW per channel at 25Ks/sec), the implantable compression circuit is well suited for intra-cortical neural interface applications.