FPGA-Based Subset Sum Delay Lines

The programmable delay line is one of the key components in automatic test equipment. Recently, implementation of programmable delay lines on FPGAs has drawn growing attention due to the flexibility and reconfiguration capability that FPGAs provide. In this work, we propose the subset sum delay line...

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Bibliographic Details
Published in2014 IEEE 23rd Asian Test Symposium pp. 287 - 291
Main Authors Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2014
Subjects
ATE
Delay lines
Delays
Dynamic range
Field programmable gate arrays
FPGA
Histograms
programmable delay line
Routing
subset sum
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Summary:The programmable delay line is one of the key components in automatic test equipment. Recently, implementation of programmable delay lines on FPGAs has drawn growing attention due to the flexibility and reconfiguration capability that FPGAs provide. In this work, we propose the subset sum delay line (SSDL) architecture for FPGA-based delay lines. The SSDL architecture takes advantage of the inevitable FPGA process variations, structure irregularities and routing uncertainties to realize high-quality FPGA-based delay lines. Furthermore, compared to previous FPGA-based delay lines, the SSDL architecture is FPGA independent, this substantially enhances its portability across different FPGA generations and suppliers. An SSDL is realized on Alter a Cyclone II FPGA. Measurement results show that it achieves 76 ps resolution and has a dynamic range of 32 ns.
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2014.60