Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers

The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2 m ) using GF(2) models of its logic gates. We define a forward variable order...

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Bibliographic Details
Published in2018 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
Main Authors Tiankai Su, Yasin, Atif, Cunxi Yu, Ciesielski, Maciej
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2018
Subjects
Arithmetic circuits
Computer Algebra
Computer bugs
Cryptography
Debugging
Formal verification
Galois Field
Galois fields
Integrated circuit modeling
Logic Debugging
Logic gates
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Summary:The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2 m ) using GF(2) models of its logic gates. We define a forward variable order "FO >" and the rules of forward reduction that enable verification, bug detection, and automatic bug correction in the circuit. By analyzing the remainder generated by forward reduction, the method can determine whether the circuit is buggy, and finds the location and the type of the bug. The experiments performed on Mastrovito and Montgomery multipliers show that our debugging method is independent of the location of the bug(s) and the debugging time is comparable to the time needed to verify the bug-free circuit.
ISSN:2379-447X
DOI:10.1109/ISCAS.2018.8351397