Planar dual gate oxide LDMOS structures in 180nm power management technology

This paper presents a 20V-rated planar dual gate oxide NLDMOS power device structure fabricated in a 180nm power management technology. The performance of the planar dual gate device structure is compared to a conventional STI-based device and it is shown that the planar dual gate structure has supe...

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Published in2012 24th International Symposium on Power Semiconductor Devices and ICs pp. 405 - 408
Main Authors Sharma, S., Letavic, T., Yun Shi, Loiseau, A., Monaghan, J.-E, Feilchenfeld, N., Phelps, R., Lamothe, C., Cook, D., Dunn, J., Roerher, G., Nauschnig, H., Minixhofer, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2012
Subjects
Batteries
dual gate oxide
Electric fields
forward safe operating area
hot carrier induced drift
Hot carriers
LDMOS
Logic gates
Performance evaluation
Reliability
Semiconductor device measurement
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Summary:This paper presents a 20V-rated planar dual gate oxide NLDMOS power device structure fabricated in a 180nm power management technology. The performance of the planar dual gate device structure is compared to a conventional STI-based device and it is shown that the planar dual gate structure has superior BV ds -R sp , g m , HCI reliability, and forward safe operating area figures-of-merit. The planar dual gate structure exhibits BV ds =32V/14 mΩ.mm 2 specific on-resistance (and BV ds =20V/7.5mΩ.mm 2 for a drift length scaled version), hot carrier reliability in excess of 10 years analog lifetime in all bias regimes, and a linear forward IV characteristic. The planar dual gate architecture is scalable in rated voltage from 7V to 24V, and is an ideal component for the integration of USB switch, battery charging, backlighting, and PA envelope tracking mobile applications.
ISBN:9781457715945
1457715945
ISSN:1063-6854
1946-0201
DOI:10.1109/ISPSD.2012.6229107