Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement

A time-to-digital converter (TDC) utilizing a vernier delay line (VDL) technique has relatively large timing errors when the mismatch of the vernier delay is large. In order to overcome this problem, we propose a technique for compensating the vernier delay mismatch using multiple ring oscillation m...

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Bibliographic Details
Published in2008 IEEE Symposium on VLSI Circuits pp. 166 - 167
Main Authors Hashimoto, T., Yamazaki, H., Muramatsu, A., Sato, T., Inoue, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2008
Subjects
Calibration
Delay
Delay lines
Jitter
Logic gates
on-chip jitter measurement
on-die jitter measurement
Phase measurement
time-to-digital converter
Timing
vernier delay line
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Summary:A time-to-digital converter (TDC) utilizing a vernier delay line (VDL) technique has relatively large timing errors when the mismatch of the vernier delay is large. In order to overcome this problem, we propose a technique for compensating the vernier delay mismatch using multiple ring oscillation measurements of VDL. We verified it using an on-die jitter measurement circuit implemented in 90 nm CMOS technology and 0.880 ps timing resolution was obtained experimentally.
ISBN:1424418046
9781424418046
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2008.4585992