Reconfigurable ECC for adaptive protection of memory

• Published in: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1085 - 1088
• Main Authors: Basak, Abhishek, Paul, Somnath, Jangwon Park, Jongsun Park, Bhunia, Swarup
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2013
• Subjects: Decoding; Error correction; Error correction codes; Integrated circuit reliability; Resource management; Runtime
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2013.6674841

Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundancy) remain effective in healing manufacturing defects and process variation induced failures in nanoscale memory. They are, however, not effective in improving robustness under various run-time failures. Increasing run-time failures in memory, specifically in case of low-voltage low-power memory, has emerged as a major design challenge. Traditionally, a uniform worst-case protection using Error Correction Code (ECC) is used for all blocks in a large memory array for runt-time error resiliency. However, with both spatial and temporal shift in intrinsic reliability of a memory block, such uniform protection can be unattractive in terms of either ECC overhead or protection level. We propose a novel Reconfigurable ECC approach, which can adapt, in space and time, to varying reliability of memory blocks by using an ECC that can provide the right amount of protection for a memory block at a given time. We show that such an approach is extremely effective in diverse applications.