An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities

The standardized scalable video coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware archit...

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Bibliographic Details
Published in2009 16th IEEE International Conference on Image Processing (ICIP) pp. 2661 - 2664
Main Authors Narvekar, N.D., Konnanath, B., Mehta, S., Chintalapati, S., AlKamal, I., Chakrabarti, C., Karam, L.J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2009
Subjects
Application specific integrated circuits
Automatic voltage control
CGS
Computer architecture
decoder architecture
Decoding
H.264/AVC
Hardware
Memory architecture
Memory management
Scalability
Scalable Video Coding (SVC)
Static VAr compensators
Video coding
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Summary:The standardized scalable video coding (SVC) extension of H.264/AVC achieves significant improvements in coding efficiency relative to the scalable profiles of prior video coding standards, but its computational complexity and memory access requirements make the design of a low power hardware architecture a challenging task. This paper presents an SVC decoder architecture supporting spatial and coarse-grained quality scalability. The architecture optimizes the size of the on-chip memory and reduces the power-consuming and time-intensive external memory accesses.
ISBN:9781424456536
1424456533
ISSN:1522-4880
2381-8549
DOI:10.1109/ICIP.2009.5414130