A Dynamic Link-Width Optimization for Network-on-Chip

Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Diffe...

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Bibliographic Details
Published in2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications Vol. 2; pp. 106 - 108
Main Authors Daihan Wang, Koibuchi, M., Yoneda, T., Matsutani, H., Amano, H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2011
Subjects
Computer architecture
Hardware
Image edge detection
Network-on-Chip
Optimization
Resource management
router architecture
System-on-a-chip
Topology
traffic analysis
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Summary:Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous No Coptimization approaches, in which the optimization is almost performed in the NoC design step, the proposed method achieves a dynamical link-width optimization at run-time.
ISBN:9781457711183
1457711184
ISSN:2325-1271
DOI:10.1109/RTCSA.2011.60