A 4mW 3-tap 10 Gb/s decision feedback equalizer

A half-rate low-power 3-tap decision feedback equalizer (DFE) was designed in 90-nm CMOS technology. An improved switched-capacitor-based summer architecture is used in the front-end sample-and-hold to speculate the first feedback tap. Other two taps are canceled using current summation technique. F...

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Bibliographic Details
Published in2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1 - 4
Main Authors Payandehnia, P., Abbasfar, A., Sheikhaei, S., Forouzandeh, B., Nanbakhsh, K., Eghbali, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2011
Subjects
CMOS integrated circuits
CMOS technology
Decision feedback equalizers
Flip-flops
Multiplexing
Silicon
Switches
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Summary:A half-rate low-power 3-tap decision feedback equalizer (DFE) was designed in 90-nm CMOS technology. An improved switched-capacitor-based summer architecture is used in the front-end sample-and-hold to speculate the first feedback tap. Other two taps are canceled using current summation technique. Further power consumption reduction is achieved by using sense-amplifier-based slicer and pass-gate multiplexer instead of CML architecture. An accurate characterization of DFE, based on Least Square Estimation and using random sequence, with certain probabilistic characteristics suitable for intended operating conditions, is described. The Proposed 3-tap DFE consumes 4 mW from a 1.2 V supply when equalizing 10 Gb/s data passed over a 10" NELCO channel with 15 dB of loss at 5 GHz.
ISBN:9781612848563
1612848567
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2011.6026319