Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic

• Published in: Thirteenth International Symposium on Quality Electronic Design (ISQED) pp. 63 - 72
• Main Authors: Bao Liu, Xuemei Chen, Teshome, F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2012
• Subjects: Clocks; Color; Latches; Logic gates; Nanoscale devices; Timing; Very large scale integration
• ISBN: 9781467310345; 1467310344
• ISSN: 1948-3287
• DOI: 10.1109/ISQED.2012.6187475

Nanoscale VLSI systems are subject to increasingly prevalent catastrophic defects, soft errors, and significant parametric variations, which cannot be reduced below certain levels according to quantum physics, and must be handled by new design methods. In this paper, we leverage the existing fault-secure logic design techniques, and propose resilient and adaptive-performance (RAP) logic based on delay-insensitive (DI) code and inversion-free logic. RAP logic clears all timing errors and achieves adaptive maximum performance in the absence of external soft errors at a higher area/power cost compared with the existing logic paradigms. Our experimental results further demonstrate that dual-rail static (Domino) RAP logic outperforms alternative delay-insensitive (DI) code-based static (Domino) RAP logic with less area, higher performance and lower power consumption in all test cases, and achieves an average of 2.29(2.41)× performance boost, 2.12(1.91)× layout area and 2.38(2.34)× power consumption compared with the traditional minimum area static logic based on the Nangate 45nm open cell library.