Three Dimensional (3D) n-gate MOSFET

The concept of a three-dimensional (3D) n-gate MOSFET device SOI substrate has been proposed and developed in this work. This device consists of a rounded surface channel with gate extensions into the buried oxide for improved subthreshold behavior. The fabrication steps are compatible with the bulk...

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Bibliographic Details
Published in2007 International Symposium on Integrated Circuits pp. 33 - 36
Main Authors Theng, A.L., Goh, W.L., Chan, Y.T., Tee, K.M., Chan, L., Ng, C.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2007
Subjects
CMOS process
Electrodes
Etching
Fabrication
MOS Devices
MOSFET circuits
Oxidation
Rapid thermal processing
Semiconductor device manufacture
Shape
Silicon
silicon-on-insulator(SOI)
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Summary:The concept of a three-dimensional (3D) n-gate MOSFET device SOI substrate has been proposed and developed in this work. This device consists of a rounded surface channel with gate extensions into the buried oxide for improved subthreshold behavior. The fabrication steps are compatible with the bulk CMOS process and it requires a mere addition of a reactive ion etching (RIE) etch step. Hence, the proposed n-gate transistor can be a viable replacement for bulk transistor in the near future.
ISBN:9781424407965
1424407966
ISSN:2325-0631
DOI:10.1109/ISICIR.2007.4441789