SIPT: Speculatively Indexed, Physically Tagged Caches

• Published in: 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) pp. 118 - 130
• Main Authors: Zheng, Tianhao, Zhu, Haishan, Erez, Mattan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2018
• Subjects: Cache and memory architectures; Coherence; Computer architecture; Hardware; Indexing; Innovative hardware/software trade offs; Processor architecture; Program processors
• ISSN: 2378-203X
• DOI: 10.1109/HPCA.2018.00020

First-level (L1) data cache access latency is critical to performance because it services the vast majority of loads and stores. To keep L1 latency low while ensuring low-complexity and simple-to-verify operation, current processors most-typically utilize a virtually-indexed physically-tagged (VIPT) cache architecture. While VIPT caches decrease latency by proceeding with cache access and address translation concurrently, each cache way is constrained by the size of a virtual page. Thus, larger L1 caches are highly-associative, which degrades their access latency and energy. We propose speculatively-indexed physically-tagged (SIPT) caches to enable simultaneously larger, faster, and more efficient L1 caches. A SIPT cache speculates on the value of a few address bits beyond the page offset concurrently with address translation, maintaining the overall safe and reliable architecture of a VIPT cache while eliminating the VIPT design constraints. SIPT is a purely microarchitectural approach that can be used with any software and for all accesses. We evaluate SIPT with simulations of applications under standard Linux. SIPT improves performance by 8.1% on average and reduces total cache-hierarchy energy by 15.6%.