An undersampling 14-bit cyclic ADC

An undersampling 14-bit 357 kSps cyclic ADC is designed for radio frequency identification (RFID) transceiver system. Modified passive capacitor error-average (PCEA) technique is adopted for high accuracy. Opamp sharing and the removal of front-end SHA are utilized for low power dissipation and smal...

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Bibliographic Details
Published in2009 IEEE 8th International Conference on ASIC pp. 211 - 214
Main Authors Weitao Li, Fule Li, Dandan Guo, Chun Zhang, Zhihua Wang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2009
Subjects
Baseband
Capacitors
Clocks
Counting circuits
cyclic ADC
Frequency
Microelectronics
modified PCEA
opamp sharing
Power dissipation
Radiofrequency identification
RFID tags
Transceivers
undersampling
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Summary:An undersampling 14-bit 357 kSps cyclic ADC is designed for radio frequency identification (RFID) transceiver system. Modified passive capacitor error-average (PCEA) technique is adopted for high accuracy. Opamp sharing and the removal of front-end SHA are utilized for low power dissipation and small chip area. The proposed chip is fabricated in a 180 nm CMOS process, and it occupies 0.65 mm × 1.6 mm. With 2.431 MHz input, the ADC achieves 70.4 dB signal-to-noise and distortion ration (SNDR), 85.6 dB spurious free dynamic range (SFDR) and 11.4 effective number of bits (ENOB). When the input frequency increases to 15.59 MHz, the measured SNDR, SFDR and ENOB are 67.3 dB, 88.1 dB and 10.9 bit, respectively. With 3 V supply, it consums 4.2 mW with FOM of 4.3 pJ/Step.
ISBN:9781424438693
1424438691
1424438683
9781424438686
ISSN:2162-7541
2162-755X
DOI:10.1109/ASICON.2009.5351493