Processor Scheduler for Multi-Service Routers

• Published in: 2006 27th IEEE International Real-Time Systems Symposium (RTSS'06) pp. 225 - 235
• Main Authors: Kokku, R., Shevade, U., Shah, N., Mahimkar, A., Taewon Cho, Vin, H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2006
• Subjects: Delay effects; Fluctuations; IP networks; Laboratories; National electric code; Packet switching; Processor scheduling; Switches; Throughput; Web and internet services
• ISBN: 0769527612; 9780769527611
• ISSN: 1052-8725
• DOI: 10.1109/RTSS.2006.38

In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A scheduler for such routers is required to maximize the number of packets processed within a given delay tolerance, while isolating the performance of services from each other. The design of such a scheduler is novel and challenging because of three domain-specific characteristics: (1) difficult-to-predict and high packet arrival rates, (2) small delay tolerances of packets, and (3) significant overheads for switching allocation of processors from one service to another. These characteristics require that the scheduler be agile and wary simultaneously. Whereas agility enables the scheduler to react quickly to fluctuations in packet arrival rates, wariness prevents the scheduler from wasting computational resources in unnecessary context switches. We demonstrate that by balancing agility and wariness, Everest, as compared to conventional schedulers, reduces by more than an order of magnitude the average delay and the percentage of packets that experience delays greater than their tolerance. We describe a prototype implementation of Everest on Intel's IXP2400 network processor