Effect of parametric randomness on reliability analysis of wafer-level chip-scale packages

• Published in: 2008 International Conference on Electronic Materials and Packaging pp. 297 - 300
• Main Authors: Wen-Fang Wu, Teng-Kai Hsu, Chih-Yen Su, Yao-Chung Chen, Yao Hsu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2008
• Subjects: Analytical models; Chip scale packaging; Fatigue; Finite element methods; Life testing; Predictive models; Probability distribution; Prototypes; Random variables; Wafer scale integration
• ISBN: 9781424436200; 1424436206
• DOI: 10.1109/EMAP.2008.4784287

To obtain probability distribution of random life of a package such as that shown in prototyping testing, some parameters involved in the finite element and life prediction analyses of a certain type of wafer-level chip-scale package (WLCSP) are considered random variables in the present paper. First, the solder-bump size of the package is modeled as a random variable in consideration of real manufacturing tolerance. Its effect on the random fatigue life prediction and quantitative reliability assessment of the package is investigated and discussed through statistical analysis of the simulation result. Secondly, parameters appearing in the modified Coffin-Manson equation are modeled as random variables in consideration of data scatter of the material test result. Their effects on random fatigue life prediction of the package are investigated and discussed through both analytical derivation and simulations. The degrees of influence of all studied parameters on the fatigue life and reliability prediction of the package are discussed in detail in the paper.