Bias-line compensation in multi-stage amplifiers

• Published in: 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1 - 4
• Main Authors: Surkanti, P. R., Furth, P. M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2011
• Subjects: Bandwidth; Hardware; Transistors
• ISBN: 9781612848563; 1612848567
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2011.6026337

In this paper, a novel bias-line compensation (BLC) using inverting current buffer for multi-stage amplifiers is proposed. This technique uses a compensation capacitor connected between the output node and low-impedance bias line, which helps in increasing the bandwidth and improving PSRR. The proposed technique is implemented in a widely-adopted low-voltage, high-gain and wide-swing pseudo-class AB amplifier [1]. The amplifier is conventionally compensated with reverse-nested Miller compensation. The results show that bias-line compensation improves the bandwidth by 50% and PSRR by 5dB with ±1.25V power supplies. The amplifier with bias-line compensation is stable for a capacitive load in the range of 1pF to 200pF. The chip was fabricated in a 0.5μm 2P3M process. Measurement results validate the effectiveness of the proposed method.