Design for manufacturability and reliability for TSV-based 3D ICs

• Published in: 17th Asia and South Pacific Design Automation Conference pp. 750 - 755
• Main Authors: Pan, D. Z., Sung Kyu Lim, Athikulwongse, K., Moongon Jung, Mitra, J., Jiwoo Pak, Pathak, M., Jae-seok Yang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2012
• Subjects: Electromigration; Reliability; Silicon; Tensile stress; Three dimensional displays; Through-silicon vias
• ISBN: 9781467307703; 146730770X
• ISSN: 2153-6961; 2153-697X
• DOI: 10.1109/ASPDAC.2012.6165055

The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for 3D IC manufacturability and reliability. In particular, TSVs in 3D IC may cause significant thermal mechanical stress, which not only results in systematic mobility/performance variations, but also leads to mechanical reliability concerns such as interfacial cracking. Meanwhile, the huge dimensional gaps between TSV, on-chip wires, and bonding/packaging all lead to new electromigration concerns. Thus full-chip/package modeling and physical design tools need to be developed to achieve more reliable 3D IC integration. In this paper, we will discuss some key design for manufacturability and reliability challenges and possible solutions for TSV-based 3D IC integration, as well as future research directions.