150nm SOI embedded SRAMs with very low SER

A split word line design technique that improves the soft error rate (SER) of high performance 150nm SOI embedded SRAMs is presented along with SER results.

Saved in:
Bibliographic Details
Published in2005 IEEE International SOI Conference Proceedings pp. 188 - 190
Main Authors Nelson, D.K., Liu, H., Golke, K., Kohli, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Charge carrier processes
Delay effects
Error analysis
Neutrons
Protection
Random access memory
Silicon
Single event upset
Testing
Voltage
Online AccessGet full text

Cover

More Information
Summary:A split word line design technique that improves the soft error rate (SER) of high performance 150nm SOI embedded SRAMs is presented along with SER results.
ISBN:0780392124
9780780392120
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2005.1563583