On the Configurable Multiprocessor SoC Platform with Crossbar Switch

• Published in: APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems pp. 1087 - 1090
• Main Authors: Byung-Joo Hong, Koon-Shik Cho, Seung-Hyun Kang, Suk-Yoon Lee, Jun-Dong Cho
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2006
• Subjects: Bandwidth; Communication switching; Crossbar Switch; Digital video broadcasting; DVB-T; H.264; Intellectual property; Master-slave; Multiprocessor; NoC; Protocols; Scalability; SoC; Switches; System-on-a-chip; Testing
• ISBN: 9781424403868; 9781424403875; 1424403871; 1424403863
• DOI: 10.1109/APCCAS.2006.342310

As the number of intellectual properties (IP) embedded in system on chip increases, more efficient on-chip-communication architecture is required. conventional on-chip-bus (OCB) cannot successfully deal with large data bandwidth and bottleneck problem. Therefore, a network structure with simple communication protocol will resolve the problems caused by OCB-based system. In this paper, the authors implement a crossbar switch architecture suitable for multiprocessor platform. The proposed crossbar switch architecture is configurable by using the parameters such as the number of communication masters and slaves so as to facilitate the scalability and flexibility. This presented crossbar switch is designed at register transfer level and tested in our multiprocessor platform called "VADA (verification platform with ARM and DSP-based multiprocessor architecture)". To check the performance of the proposed architecture, DVB-T (digital video broadcasting-terrestrial) baseband receiver is implemented and verified with Seamless CVEtrade, HW/SW co-verification tool. The proposed configurable multiprocessor platform with crossbar switch architecture can be also applied to an advanced CODEC such as H.264