Failure mechanism of high-voltage isolated lateral diffused NMOS under high-current events

In this study, the mechanism of the effect of a high-voltage (HV) NWell guardring (NW-GR) on the electrostatic discharge (ESD) robustness of the HV isolated lateral diffused NMOS (HV ISO-LDNMOS) is investigated. The device fails on low-voltage ESD zapping events when the HVNW-GR is connected to the...

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Bibliographic Details
Published in2016 IEEE International Reliability Physics Symposium (IRPS) pp. EL-2-1 - EL-2-5
Main Authors Cheng-Hsu Wu, Chen-Hsin Lien, Jian-Hsing Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2016
Subjects
Deeply depleted
Electrostatic discharge
Electrostatic discharges
Failure analysis
Junctions
Logic gates
Robustness
Secondary breakdown current
Snapback
Stress
Transistors
Trigger voltage
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Summary:In this study, the mechanism of the effect of a high-voltage (HV) NWell guardring (NW-GR) on the electrostatic discharge (ESD) robustness of the HV isolated lateral diffused NMOS (HV ISO-LDNMOS) is investigated. The device fails on low-voltage ESD zapping events when the HVNW-GR is connected to the drain, whereas the device passes these events once it is floated.
ISSN:1938-1891
DOI:10.1109/IRPS.2016.7574603