A reconfigurable arbiter for SOC applications

• Published in: APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems pp. 713 - 716
• Main Authors: Ching-Chien Yuan, Yu-Jung Huang, Shih-Jhe Lin, Kai-hsiang Huang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2008
• Subjects: Algorithm design and analysis; Analytical models; Content management; Degradation; Heuristic algorithms; Performance analysis; Performance gain; Resource management; System performance; Telecommunication traffic
• ISBN: 9781424423415; 1424423414
• DOI: 10.1109/APCCAS.2008.4746123

For a SOC communication architecture, an efficient arbitration algorithm to resolve contention schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation.This paper presents the design and performance analysis of an arbiter with a hybrid arbitration algorithm. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain better system performance is described. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The results indicate a better performance can be achieved as compared with the traditional arbitration assignment scheme. Based on the performance analysis, the hybrid arbitration can be custom-tuned to meet the design requirements. The implementation of the arbiter with hybrid arbitration scheme for system on chip applications is also explained. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys design complier with a TSMC 0.18 mum cell library.