FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm
In this paper, we introduce a field-programmable gate array (FPGA) hardware architecture for the realization of an algorithm for computing the eigenvalue decomposition (EVD) of para-Hermitian polynomial matrices. Specifically, we develop a parallelized version of the second-order sequential best rot...
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Published in | 2012 International Conference on Field-Programmable Technology pp. 135 - 140 |
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Main Authors | , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.12.2012
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Subjects | |
Online Access | Get full text |
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Summary: | In this paper, we introduce a field-programmable gate array (FPGA) hardware architecture for the realization of an algorithm for computing the eigenvalue decomposition (EVD) of para-Hermitian polynomial matrices. Specifically, we develop a parallelized version of the second-order sequential best rotation (SBR2) algorithm for polynomial matrix EVD (PEVD). The proposed algorithm is an extension of the parallel Jacobi method to para-Hermitian polynomial matrices, as such it is the first architecture devoted to PEVD. Hardware implementation of the algorithm is achieved via a highly pipelined, non-systolic FPGA architecture. The proposed architecture is scalable in terms of the size of the input para-Hermitian matrix. We demonstrate the decomposition accuracy of the architecture through FPGA-in-the-loop hardware co-simulations. Results confirm that the proposed solution gives low execution times while reducing the number of resources required from the FPGA. |
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ISBN: | 1467328464 9781467328463 |
DOI: | 10.1109/FPT.2012.6412125 |