Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions

A recent decision diagram-based algorithm was able to generate test patterns for each sensitizable path delay fault. Although scalable this approach results to prohibitively long test sets. This paper presents a novel technique to intelligently select paths for compaction. It guarantees optimal comp...

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Bibliographic Details
Published in2009 27th IEEE VLSI Test Symposium pp. 140 - 145
Main Authors Flanigan, E., Tragoudas, S., Abdulrahman, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2009
Subjects
Automatic test pattern generation
Benchmark testing
Boolean functions
Circuit faults
Circuit testing
Compaction
Data structures
Delay
PDF
Robustness
Test pattern generators
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ISBN0769535984
9780769535982
ISSN1093-0167
DOI10.1109/VTS.2009.22

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Summary:A recent decision diagram-based algorithm was able to generate test patterns for each sensitizable path delay fault. Although scalable this approach results to prohibitively long test sets. This paper presents a novel technique to intelligently select paths for compaction. It guarantees optimal compaction subject to the order of processing faults. The compaction rate is superior to any published method, even for the small benchmarks where enumerative compaction methods have been proposed. Experimental results on the publicly available benchmarks demonstrate the scalability of the proposed method.
ISBN:0769535984
9780769535982
ISSN:1093-0167
DOI:10.1109/VTS.2009.22