Boolean technology mapping based on logic decomposition

• Published in: 16th Brazilian Symposium on Integrated Circuit Design (SBCCI 2003) pp. 35 - 40
• Main Authors: Damiani, M., Selchenko, A.Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Boolean functions; Circuits; Design automation; Libraries; Logic functions; Pattern matching; Space technology; Timing; Tree graphs; Vegetation mapping
• ISBN: 076952009X; 9780769520094
• DOI: 10.1109/SBCCI.2003.1232803

The decomposition tree of a logic function first appears in the work of Ashenhurst (Proc. Int. Symp. Theory of Switching, p.74-116, 1957). It is a canonical, treelike logic network representing the decomposition properties of that function. We present an algorithm for technology mapping based on the use of such trees for the representation of library elements. Decomposition information is also embedded in the representation of leaf-dags of the subject graph. Because library functions are represented by trees, this approach allows us to combine Boolean matching with efficient tree-based matching algorithms. In this way, Boolean matching can now be used not only for incremental optimization, but also for building the initial mapping "from scratch". Finally, we remark that by combining this method with the one of Lehman et al (IEEE Trans. on CAD/ICAS, vol.16(8), p.813-834, 1997), we are able to represent implicitly a search space of unprecedented size for a subject graph. The algorithm has been implemented in C++ in a prototype mapper, VERSE, and tested on several common synthesis benchmarks.