Chip cracks during assembly: Finding and eliminating the critical defect

• Published in: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) pp. 509 - 516
• Main Authors: Sauter, W., Kaldor, S., Clark, J., Laforte, S., McCarthy, C., Restaino, D., Casey, J., Questad, D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Assembly; Lead; Silicon; Tensile stress; Testing
• ISBN: 1612844979; 9781612844978
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2011.5898559

During the bond and assembly process of an organic module, the backside of the chip will be in tensile stress. Vertical cracking through the Silicon chip (as shown in Figure 1) can occur when the strength of the chip is lower than the stress that is applied through the bond and assembly processes and associated materials. The 2 main questions about chip cracks that have not sufficiently been answered in the past are: 1. is the problem one of stress or strength? 2. is the problem yield or reliability? In this paper we will demonstrate that the answers to these 2 questions are "strength" (i.e. lack thereof) and "yield" for the module types investigated. In this study we are reporting the investigation of an increase of chip cracks during assembly. The root cause was shown to be a wafer handling chuck and the associated process conditions in the FEOT (Front-End-Of-Tine) of the wafer fab. The chuck created microscopic defects on the wafer backside that resulted in cracked chips when the chips were assembled into modules about 3 months and several hundred process steps after the defects were originally created.