A 439K gates/10.9KB SRAM/2-328 mW dual mode video decoder supporting temporal/spatial scalable video

The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0....

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Bibliographic Details
Published in2009 IEEE Asian Solid-State Circuits Conference pp. 197 - 200
Main Authors Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jiun-In Guo, Jia-Wei Chen, Jinn-Shan Wang, Chin-Hsien Wang, Hsiang-Hui Huang, Ching-Hwa Cheng
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2009
Subjects
CMOS technology
Decoding
Design optimization
High definition video
Random access memory
Scalability
Static VAr compensators
Video coding
Videoconference
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Summary:The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 ¿m CMOS technology, it comprises 439 K gates/10.9 KB SRAM and consumes 2~328 mW in decoding CIF~HD1080 videos at 3.75~30 fps when operating at 1~150 MHz, respectively.
ISBN:1424444330
9781424444335
DOI:10.1109/ASSCC.2009.5357147