Reduction of operating voltage in organic transistor and CMOS circuit utilizing high-k dielectric

Employment of high-k dielectric is one of the most important strategies to reduce operating voltage of an integrated circuit. This paper demonstrates experiments on organic FET and CMOS circuit where the dielectric layer was constructed of P(VDF-TrFE) and PS polymer dielectric. The dielectric consta...

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Bibliographic Details
Published in2014 International Conference on Advanced Technologies for Communications (ATC 2014) pp. 383 - 386
Main Authors Toan Thanh Dao, Huyen Thanh Pham
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2014
Subjects
Artificial intelligence
CMOS integrated circuits
CMOS inverter
Equations
flexible electronics
High-k polymer dielectric
Logic gates
Manufacturing
OFET
Substrates
threshold voltage
Transistors
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Summary:Employment of high-k dielectric is one of the most important strategies to reduce operating voltage of an integrated circuit. This paper demonstrates experiments on organic FET and CMOS circuit where the dielectric layer was constructed of P(VDF-TrFE) and PS polymer dielectric. The dielectric constant of compound dielectric increased about three times in comparison with that of pristine PS. This contributes into lowering the operating voltage transistor circuit. The experimental results indicated that high-k dielectric of P(VDF-TrFE) and PS may be suitable for flexible low-power organic electronics.
ISBN:1479969559
9781479969555
ISSN:2162-1020
2162-1039
DOI:10.1109/ATC.2014.7043416