Soft error trends and mitigation techniques in memory devices

As CMOS process technology scales below 100nm, the amount of charge required to upset a gate or memory cell (Q crit ) is decreasing. Therefore, the probability that an energetic particle can generate enough charge to upset a circuit is increasing. Since these single event upsets do not damage the IC...

Full description

Saved in:
Bibliographic Details
Published in2011 Proceedings - Annual Reliability and Maintainability Symposium pp. 1 - 5
Main Author Slayman, C
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2011
Subjects
Alpha particle
Computer architecture
cosmic ray
Error analysis
Error correction codes
Neutrons
Physics
Random access memory
Reliability
single event upset
soft error
terrestrial neutron
Online AccessGet full text
ISBN9781424488575
1424488575
ISSN0149-144X
DOI10.1109/RAMS.2011.5754515

Cover

More Information
Summary:As CMOS process technology scales below 100nm, the amount of charge required to upset a gate or memory cell (Q crit ) is decreasing. Therefore, the probability that an energetic particle can generate enough charge to upset a circuit is increasing. Since these single event upsets do not damage the IC, they are called soft errors. With the proper detection and correction schemes, these particle induced soft errors can be mitigated in a way that does not impact the overall reliability of an electronic system. Since memory devices such as SRAM, DRAM and Flash comprise the largest gate counts in many designs, it is essential to understand their soft error mechanisms, characterize their soft error rates and develop effective mitigation techniques.
ISBN:9781424488575
1424488575
ISSN:0149-144X
DOI:10.1109/RAMS.2011.5754515