APA (7th ed.) Citation

Shih, Y., Lee, C., Chang, Y., Lee, P., Lin, H., Chen, Y., . . . Chang, J. (2018, June). Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. 2018 IEEE Symposium on VLSI Circuits, 79-80. https://doi.org/10.1109/VLSIC.2018.8502260

Chicago Style (17th ed.) Citation

Shih, Yi-Chun, et al. "Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time." 2018 IEEE Symposium on VLSI Circuits Jun. 2018: 79-80. https://doi.org/10.1109/VLSIC.2018.8502260.

MLA (9th ed.) Citation

Shih, Yi-Chun, et al. "Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time." 2018 IEEE Symposium on VLSI Circuits, Jun. 2018, pp. 79-80, https://doi.org/10.1109/VLSIC.2018.8502260.