A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity

A PCI Express 2.0/1.0 compatible SERDES system had been fabricated in TSMC 40 nm CMOS technology. With the implementation of one lane transceiver, PLL, and PCS, the experimental results have shown this test chip passes PCI Express 2.0/1.0 TX compliance test and RX compliance test. It also achieves r...

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Bibliographic Details
Published in2009 IEEE Asian Solid-State Circuits Conference pp. 177 - 180
Main Authors Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Tsung-Hsin Yu, Jinn-Yeh Chien, Chen, W.D., Chi-Chang Lu, Wei-Chih Chen, Fu, J., Yang, S.J., Chien-Hung Chen, Kuo-Liang Deng, Wen, C.H., Wang, L.Y.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2009
Subjects
Bit error rate
clock and data recovery
Clocks
CMOS technology
Deterministic jitter
Equalizers
Inter-symbol-interference
Jitter
Personal communication networks
Phase locked loops
Physical layer
Random jitter
Serializer-Deserializer
Testing
total jitter
Transceivers
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Summary:A PCI Express 2.0/1.0 compatible SERDES system had been fabricated in TSMC 40 nm CMOS technology. With the implementation of one lane transceiver, PLL, and PCS, the experimental results have shown this test chip passes PCI Express 2.0/1.0 TX compliance test and RX compliance test. It also achieves receiver jitter tolerance up to 0.33UI at BER of 10 -12 with stressing all spec. specified jitter sources. A compact area of 510 um * 710 um for one lane has been achieved while consuming only 125 mW from 0.9 V supply.
ISBN:1424444330
9781424444335
DOI:10.1109/ASSCC.2009.5357154