Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints

• Published in: 2012 IEEE 30th International Conference on Computer Design (ICCD) pp. 108 - 114
• Main Authors: Ghasemazar, M., Goudarzi, H., Pedram, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2012
• Subjects: Power demand; Power dissipation; Temperature control; Temperature measurement; Thermal management; Throughput; Vectors
• ISBN: 1467330515; 9781467330510
• ISSN: 1063-6404
• DOI: 10.1109/ICCD.2012.6378625

Power dissipation and die temperature have become key performance limiters in today's high-performance Chip Multiprocessors (CMPs.) Dynamic power management solutions have been proposed to manage resources in a CMP based on the measured power dissipation, performance, and die temperature of processing cores. In this paper, we develop a robust framework for power and thermal management of heterogeneous CMPs subject to variability and uncertainty in system parameters. More precisely, we first model and formulate the problem of maximizing the task throughput of a heterogeneous CMP (a.k.a., asymmetric multi-core architecture) subject to a total power budget and a per-core temperature limit. Next we develop a solution framework, called Variation-aware Power/Thermal Manager (VPTM), which is a hierarchical dynamic power and thermal management solution targeting heterogeneous CMP architectures. VPTM utilizes dynamic voltage and frequency scaling (DVFS) and core consolidation techniques to control the core power consumptions, which implicitly regulate the core temperatures. An algorithm is proposed for core consolidation and application assignment, and a convex program is formulated and solved to produce optimal DVFS settings. Finally, a feedback controller is employed to compensate for variations in key system parameters at runtime. Experimental results show highly promising performance improvements for VPTM compared to the state-of-the-art techniques.