Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era

A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthr...

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Published inESSDERC 2007 - 37th European Solid State Device Research Conference pp. 327 - 329
Main Authors Sungsam Lee, Jongchul Park, Kwangwoo Lee, Sungho Jang, Junho Lee, Hyunsook Byun, Ilgweon Kim, Yongjin Choi, Myoungseob Shim, Duheon Song, Joosung Park, Taewoo Lee, Dongho Shin, Gyoyoung Jin, Kinam Kim
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2007
Subjects
Computer aided engineering
Doping
Etching
Isolation technology
Project management
Random access memory
Scanning electron microscopy
Size control
Technological innovation
Transistors
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Summary:A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.
ISBN:1424411238
9781424411238
ISSN:1930-8876
DOI:10.1109/ESSDERC.2007.4430944