Programmable CMOS CNN chip for binary image processing

• Published in: (ICEEE). 1st International Conference on Electrical and Electronics Engineering, 2004 pp. 210 - 213
• Main Authors: Molitiar-Solis, J.E., Gomez-Castafieda, F., Moreno-Cadenas, J.A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Cellular neural networks; CMOS process; CMOS technology; Image processing; Integrated circuit modeling; Laboratories; Multiplexing; Real time systems; Silicon; Very large scale integration
• ISBN: 0780385314; 9780780385313
• DOI: 10.1109/ICEEE.2004.1433878

At present, Cellular Neural Networks (CNN) in VLSI technology are powerful parallel structures with real-time image processing capabilities. In this context it is necessary to work on a simplified CNN idea from the hardware point of view (derived from the original CNN model proposed by Chua et al.) in order to design a more feasible CNN IC with lower complexity circuits. In this work, taking into account that many binary image tasks present a linearly separable feature, the original output function can be replaced by a step function. Analog multipliers can be substituted by simple analog multiplexers and we take advantage that all the signals can be unipolar. These features reduce the complexity of the circuits but preserving the computation in selected binary-image processing tasks. The circuits in our CMOS integrated circuit belong to the class of those in the design of mixed-signal systems with current-mode representation of signal-flow. The technology for these circuits is based on the n-well, 1.2-micron CMOS process offered by MOSlS to research groups in universities.