Design of a 3-D stacked floating-point adder

• Published in: 2013 IEEE International 3D Systems Integration Conference (3DIC) pp. 1 - 4
• Main Authors: Tada, Jubee, Egawa, Ryusuke, Kobayashi, Hiroaki
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2013
• Subjects: Adders; Delays; Logic gates; Multiplexing; Silicon carbide; Three-dimensional displays; Wires
• DOI: 10.1109/3DIC.2013.6702390

Three-dimensional (3-D) stacked integrated circuit (SIC) technologies have been expected to overcome the limitation in the design of microprocessors integrated by two-dimensional (2-D) implementations. 3-D SIC technologies enable to stack multiple integrated silicon layers. In the design of 3-D stacked arithmetic units, the circuits are partitioned into several subcircuits, and each sub-circuit is placed on one layer. In order to exploit the potential of the 3-D SIC, a sophisticated partitioning should be required. In this paper, four partitioning patterns for a 3-D stacked floating-point adder are proposed, which are based on two basic ideas. One idea focuses on the structure of a 2-path floating point adder, and the other idea focuses on the large barrel shifters. Four implementations of a 3-D stacked double-precision floating-point adder are designed based on these partitioning patterns and evaluated. Experimental results show that the 3D stacked double precision floating-point adder implemented on four layers achieves up to a 16.4% delay reduction compared to the 2-D implementation.