Investigation for electromigration-induced hillock in a wafer level interconnect device

This paper investigates the electromigration induced hillock generation in a wafer level interconnect structure through a numerical approach. The driving force for electromigration induced failure includes the electron wind force, stress gradients, temperature gradients, as well as the atomic densit...

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Bibliographic Details
Published in2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) pp. 617 - 624
Main Authors Yuan Xiang Zhang, Lihua Liang, Yong Liu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2010
Subjects
Electromigration
Electrons
Geometry
Life estimation
Stress
Temperature
Testing
Time measurement
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Summary:This paper investigates the electromigration induced hillock generation in a wafer level interconnect structure through a numerical approach. The driving force for electromigration induced failure includes the electron wind force, stress gradients, temperature gradients, as well as the atomic density gradient, which were neglected in many of the existing studies on electromigration. The parameter study for the Al line geometry with different width and thickness of a standard wafer level electromigration accelerated test (SWEAT) structure is investigated. The comparison of void/hillock formation and the time to failure (TTF) life through numerical example of the SWEAT structure with the measurement result is studied and discussed. Finally, the TTF life of a hillock is defined and discussed.
ISBN:9781424464104
1424464102
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2010.5490862