LOOFA-PB: A Modified LOOFA Scheduler for Variable-Length Packet Switching

• Published in: 2007 IEEE International Conference on Communications pp. 6336 - 6343
• Main Authors: Shiravi, A., Min, P.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2007
• Subjects: Application specific integrated circuits; Communication switching; Communications Society; Cost function; Delay; Hardware; Packet switching; Scheduling algorithm; Switches; Systems engineering and theory
• ISBN: 9781424403530; 1424403537
• ISSN: 1550-3607; 1938-1883
• DOI: 10.1109/ICC.2007.1049

The LOOFA algorithm is a cell-based scheduler for CIOQ crossbar switches that can guarantee the work-conserving property in a cell-based switch if the crossbar switch works twice as fast as the line rate (speedup of two). Unfortunately, the cell based LOOFA algorithm is not work-conserving for variable- length packet switches because it interleaves the cells from different inputs to a particular output and does not necessarily serve cells belonging to a packet contiguously. Thus, the cells belonging to a variable- length packet must be reassembled at the output port before the packet can be transmitted. This requires a large buffer at the output stage, and causes extra delays. PLF, which is another suggested scheduling algorithm for variable-length packet switches, has its own limitations. PLF must use a considerable amount of memory at every crosspoint of the buffered crossbar, making the overall complexity high. In this paper we examine the work conserving property of the LOOFA and the PLF algorithms in variable-length packet switches and propose a packet-based version of the LOOFA (called the LOOFA-PB) for variable-length packets. The proposed algorithm is a (L max /2)-work- conserving algorithm and does not need a buffered crossbar or a speedup greater than two. In addition, the LOOFA-PB algorithm eliminates the need for reassembly and serves packets contiguously. As a result, it reduces the overall packet delay. Finally, eliminating the SAR functionality from the algorithm results in a smaller die size when implemented in an ASIC, and cheaper cost.