Modeling of a silicon-carbide MOSFET with focus on internal stray capacitances and inductances, and its verification

• Published in: 2017 IEEE Applied Power Electronics Conference and Exposition (APEC) pp. 2671 - 2677
• Main Authors: Mukunoki, Yasushige, Horiguchi, Takeshi, Nakayama, Yasushi, Nishizawa, Akinori, Nakamura, Yuta, Konno, Kentaro, Kuzumoto, Masaki, Akagi, Hirofumi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2017
• Subjects: Capacitance; coupling coefficient; Data models; device characterization; device modeling; gate current; gate drive circuit; Integrated circuit modeling; internal stray capacitances; Logic gates; MOSFET; Numerical models; Semiconductor device modeling; SiC-MOSFETs; stay inductances; the rate of drain-current-change; the rate of drain-source-voltage change
• ISSN: 2470-6647
• DOI: 10.1109/APEC.2017.7931076

This paper describes a compact model for an SiC-MOSFET, which features characterization and modeling of a novel drain-gate capacitor. In addition, the inner gate resistance and stay inductances of the package are evaluated and modeled by a newly-proposal method. The gate drive circuit is also modeled and involved in this simulation study. The model shows excellent agreements in steady and transient states between simulated and experimental waveforms. The comparison shows accurate reproducibility of both the rate of drain-source-voltage change and that of drain-current-change with an error of 10 % for turn-on behavior, and with a maximum error of 20 % for turn-off behavior. This successful validation indicates that the developed model is expected to open up the possibilities of the simulation study for evaluating detailed performance of SiC-MOSFETs.