An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement

• Published in: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers pp. 470 - 471
• Main Authors: Hyeok-Ki Hong, Hyun-Wook Kang, Sung, B., Choong-Hoon Lee, Choi, M., Ho-Jin Park, Seung-Tak Ryu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2013
• Subjects: Capacitance; Capacitors; Error correction; Hardware; Prototypes; Switches; Timing
• ISBN: 9781467345156; 1467345156
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2013.6487819

By taking advantage of the merits of the low power consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1-3]. However, many error sources in the 2b/cycle SAR ADCs, such as mismatches between DACs and comparators, and the signal-dependent errors from comparators, namely kickback noise and offset, make it difficult to achieve high resolution. To date, pure 2b/cycle structures operating above hundreds of MS/s have shown a somewhat limited resolution with an ENOB lower than 7 at Nyquist rates [1,2]. As a derivation of the structure, a sub-ADC could be implemented using the 2b/cycle SAR ADC structure for high resolution as in [4], at the cost of increased circuit complexity and static current flow. In this work, we present a resolution-enhancing design technique for 2b/cycle SAR ADCs with negligible hardware overhead, while relieving the requirements for the aforementioned errors: Reconfiguration from a 2b/cycle structure to a normal 1b/cycle SAR ADC with error-correction capability achieves an 8.6 ENOB from a 9b ADC.