Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis

• Published in: 2018 IEEE East-West Design & Test Symposium (EWDTS) pp. 1 - 7
• Main Authors: Lojda, Jakub, Podivinsky, Jakub, Kotasek, Zdenek
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2018
• Subjects: Benchmark testing; C++ languages; Circuit faults; Hardware design languages; Integrated circuit reliability
• ISSN: 2472-761X
• DOI: 10.1109/EWDTS.2018.8524631

During the last decades, electronic systems became an important matter of controlling many critical processes. However, those critical processes often require increased reliability. This requirement places pressure on system developers to make systems reliable. Be-cause of ever growing chip-level integration, capabilities of electronic systems are expanding, and, thus, leading to more complex system architectures, the number of man-hours needed to develop such systems is significantly increasing. Many people believe the solution is to move the development to a higher level of abstraction (e.g. an algorithm level) and use the so-called High-Level Synthesis (HLS) for this purpose. In this research, we aimed towards a decision, whether the usage of HLS impacts the resulting reliability properties of the system, and, thus, whether the HLS-generated system matches reliability properties of its corresponding VHDL-implemented version. We found out that, for the selected set of circuits, HLS performs better in terms of resource consumption, but, also, which we consider surprising, in terms of reliability. For the selected set, HLS achieved better reliability by 3.03 percentage points in contrast to the classical approach utilizing a traditional Hardware Description Language (HDL). In these experiments, no redundancy was intentionally inserted into benchmarking circuits.