Suppression of threshold voltage shift for normally-Off GaN MIS-HEMT without post deposition annealing

In this paper, we present a method of reducing threshold voltage shift for normally-off GaN MIS-HEMT by the optimization of dielectric deposition conditions. High-temperature deposition of Al 2 O 3 insulator decreases the impurities in a dielectric film, leading to small C-V and I-V hysteresis under...

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Bibliographic Details
Published in2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) pp. 411 - 414
Main Authors Kanamura, M., Ohki, T., Ozaki, S., Nishimori, M., Tomabechi, S., Kotani, J., Miyajima, T., Nakamura, N., Okamoto, N., Kikkawa, T., Watanabe, K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2013
Subjects
Aluminum gallium nitride
Aluminum oxide
Capacitance-voltage characteristics
Gallium nitride
Hysteresis
Insulators
Logic gates
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Summary:In this paper, we present a method of reducing threshold voltage shift for normally-off GaN MIS-HEMT by the optimization of dielectric deposition conditions. High-temperature deposition of Al 2 O 3 insulator decreases the impurities in a dielectric film, leading to small C-V and I-V hysteresis under large positive gate voltage operation. Moreover, Al 2 O 3 deposited at high temperature achieve high quality interface and bulk without post deposition annealing (PDA), preventing the degradation of electrodes and crystallization of insulator film. The fabricated device shows small C-V and I-V hysteresis, with a breakdown voltage of greater than 600 V.
ISBN:9781467351348
1467351342
ISSN:1063-6854
1946-0201
DOI:10.1109/ISPSD.2013.6694432