K-way partitioning based packing for FPGA logic blocks without input bandwidth constraint

Cluster-based logic blocks from most commercial FPGA products do not have an input bandwidth constraint, i.e., limiting the number of signals going from routing channels into the block. We show that high quality packing for such logic blocks can be easily achieved based on k-way partitioning. We imp...

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Bibliographic Details
Published in2012 International Conference on Field-Programmable Technology pp. 8 - 15
Main Author Wenyi Feng
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2012
Subjects
Bandwidth
Clustering algorithms
Cost function
Delay
Field programmable gate arrays
Routing
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Summary:Cluster-based logic blocks from most commercial FPGA products do not have an input bandwidth constraint, i.e., limiting the number of signals going from routing channels into the block. We show that high quality packing for such logic blocks can be easily achieved based on k-way partitioning. We implemented 2 such packing tools: PPack (routability-only) and its timing driven version TPPack. Experimental results show that they have superior quality. Compared to T-VPack, PPack reduces total wire-length and minimal channel width by 22.6% and 22.6% with a 1.9% performance gain; TPPack reduces total wire-length and minimal channel width by 20.0% and 20.2% with a 9.0% performance gain. These results are achieved at no loss of utilization.
ISBN:1467328464
9781467328463
DOI:10.1109/FPT.2012.6412103