Footprint design optimization in SiGe BiCMOS SOI technology

Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Ea...

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Bibliographic Details
Published in2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting pp. 208 - 211
Main Authors Tianbing Chen, Babcock, J., Yen Nguyen, Greig, W., Lavrovskaya, N., Thibeault, T., Ruby, S., Adler, S., Krakowski, T., Jonggook Kim, Sadovnikov, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2008
Subjects
Electrical resistance measurement
Electron tubes
Extraterrestrial measurements
footprint
Heterojunction bipolar transistors
impact ionization
safe operating area
self heating
SiGe HBT
Silicon germanium
Thermal resistance
Transistors
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Summary:Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak f T and noise figure improves slightly with footprint, and peak f MAX improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for BiCMOS devices on SOI is also proposed.
ISBN:9781424427253
1424427258
ISSN:1088-9299
2378-590X
DOI:10.1109/BIPOL.2008.4662745