Voltage controlled oscillator area reduction in nano-scale CMOS

• Published in: 2014 IEEE Radio Frequency Integrated Circuits Symposium pp. 421 - 424
• Main Authors: Jha, Amit, Liao, Ken, Yeap, Geoffrey, Kenneth, K. O.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2014
• Subjects: area efficiency; CMOS; CMOS integrated circuits; inductor; Inductors; Phase noise; Tuning; Varactors; voltage controlled oscillator; Voltage-controlled oscillators
• ISBN: 1479938629; 9781479938629
• ISSN: 1529-2517; 2375-0995
• DOI: 10.1109/RFIC.2014.6851757

A 4.3-5.6 GHz (26% tuning range) voltage controlled oscillator (VCO) incorporating MOS bypass capacitors, MOS varactors, cross-coupled transistors, a current source and buffers underneath an inductor is demonstrated in 65-nm CMOS. Use of a simple inverter based buffer enables straightforward placement under an inductor. The bypass capacitors and other components are used to form a patterned ground shield that improves inductor Q. The measured phase noise of the VCO is -117dBc/Hz at 1 MHz offset from a 4.3GHz carrier. The VCO power consumption is 4 mW. The circuit occupies an area of 14,400 μm 2 , and exhibits FOMa and FOMta of -202 and -210 dB, respectively. The FOMta is at least 10 dB better than the others in the literature. The area is ~3X smaller compared to that of the VCO with all the components outside of the inductor.