Fault tolerant cellular array design for nanoscale technologies

• Published in: 2010 42nd Southeastern Symposium on System Theory (SSST) pp. 258 - 262
• Main Author: Hoe, David H K
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2010
• Subjects: Arithmetic; Array signal processing; Fabrics; Fault tolerance; Field programmable gate arrays; Logic arrays; Logic devices; Logic functions; Reconfigurable logic; Table lookup
• ISBN: 1424456908; 9781424456901
• ISSN: 0094-2898; 2161-8135
• DOI: 10.1109/SSST.2010.5442822

A cellular array architecture suitable for implementing fault-tolerant logic on nanoscale fabrics is described in this paper. A simple logic cell that is optimized for arithmetic logic functions allows efficient implementation of signal processing functions. Compared to the typical look-up table (LUT) approach used in FPGAs, the proposed logic block has decreased flexibility in terms of reconfigurability. However, the simpler structure and reduced number of configuration bits results in improved fault tolerant capability. Such a design tradeoff is suitable for nanotechnology implementations where there are a massive number of devices but also increased susceptibility to transient and permanent faults. A hierarchical approach to clustering the cells provides for an optimum number of spare cells to be distributed throughout the array, allowing for efficient self-healing capability.