Investigation of 300 mm TSV wafer flatness with via middle scheme

• Published in: 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) pp. 240 - 243
• Main Authors: Li Hongyu, Xie Jielin, Li Weihong, Teo Keng Hwa
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2012
• Subjects: Annealing; Metals; Solids; Stress; Surface treatment; Through-silicon vias
• ISBN: 9781467345538; 1467345539
• DOI: 10.1109/EPTC.2012.6507085

Wafer flatness was monitored and investigated within TSV process development from TSV liner deposition to Cu CMP. The highest wafer bow height (455μm) was observed after TSV Cu annealing (410°C, 30mins) and second wafer bow height (-228μm) was shown after barrier metal and Cu seed sputtering. 5KÅ Ti barrier metal and 8KÅ Cu seed contributed bow height within TSV Cu annealing. To study the contribution of 5KÅ Ti and 8KÅ Cu seed, those films were separately deposited on blank wafers. 5KÅ Ti induced more wafer warpage compare with 8KÅ Cu base on the FSM measurement results. PVD Ti deposition chamber was improved and process was optimized. TSV PVD process stress on wafer bow height is reduced from -221.6μm to -58.1μm while TSV was solid filled with Cu.