Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops

In this paper, a novel low power flip-flop circuit which is faster than the previous one is proposed. This circuit is applied in two cases, single edge triggered, and double edge triggered. One which works at single edge is called high speed modified hybrid latch flip-flop (HSMHLFF), and another one...

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Bibliographic Details
Published inAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems pp. 1383 - 1386
Main Authors Aezinia, F., Najafzadeh, S., Ali Afzali-Kusha
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2006
Subjects
Circuit simulation
Clocks
CMOS technology
Delay
Digital circuits
Energy consumption
flip-flop
Flip-flops
high speed
Latches
low power
Timing
Very large scale integration
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Summary:In this paper, a novel low power flip-flop circuit which is faster than the previous one is proposed. This circuit is applied in two cases, single edge triggered, and double edge triggered. One which works at single edge is called high speed modified hybrid latch flip-flop (HSMHLFF), and another one which works at double edge is called high speed double edge triggered modified hybrid latch flip-flop (HSDMHLFF). In this proposed design, path between clock and output becomes shorter than the pervious one. This leads to lower delay and power dissipation. HSMHLFF and HSDMHLFF are simulated using HSPICE in 180nm bulk CMOS technology. Compared to the earliest work, the new circuits show better speed and power consumption
ISBN:9781424403868
9781424403875
1424403871
1424403863
DOI:10.1109/APCCAS.2006.342458