Design and FPGA implementation of a 100 Gbit/s optical transport network processor

This paper presents the design and architecture of an OTN Processor, fully implemented in FPGA devices, that provides transport for Ethernet traffic running at 100 Gbit/s into a long-haul optical network, and regeneration of that OTN signal along the path. In addition to the OTN structure overview,...

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Bibliographic Details
Published in2013 23rd International Conference on Field programmable Logic and Applications pp. 1 - 4
Main Authors Bernardo, Rodrigo, Salvador, Arley H., Mobilon, Eduardo, Monte, Luis R., Boisclair, Stephane, Warshawsky, Avrum
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2013
Subjects
Adaptive optics
Clocks
Decoding
Field programmable gate arrays
Forward error correction
Repeaters
Transponders
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Summary:This paper presents the design and architecture of an OTN Processor, fully implemented in FPGA devices, that provides transport for Ethernet traffic running at 100 Gbit/s into a long-haul optical network, and regeneration of that OTN signal along the path. In addition to the OTN structure overview, we show how the data are synchronized in the ingress interface, the rate justification and mapping mechanisms, the architecture of the FEC codec, and the FPGAs resource usage. The newest FPGAs allow flexibility and optimal performance for high-speed and high-density designs, as presented in this work. An FPGA platform was used to demonstrate the developed applications in the lab.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2013.6645601